www.clare.com ds-CPC5602-r07 1 CPC5602 n-channel depletion mode fet rohs 2002/95/ec e 3 pb www.clare.com part number description CPC5602c n-channel depletion mode fet, sot-223 pkg. cut-tape, available in quantities of 200, 300, 400, 500, and 600 CPC5602ctr n-channel depletion mode fet, sot-223 pkg. tape and reel (1000/reel) applications features description ordering information package pinout ? support component for litelink? data access arrangement (daa) ? telecommunications ? normally on switches ? ignition modules ? converters ? security ? power supplies ? 350v drain-to-source voltage ? depletion mode device offers low r ds(on) at cold temperatures ? low on-resistance: 8 ? (typical) @ 25c ? low v gs(off) voltage: -2.0v to -3.6v ? high input impedance ? low input and output leakage ? small package size sot-223 ? pc card (pcmcia) compatible ? pcb space and cost savings the CPC5602 is an n-channel depletion mode field effect transistor (fet) that utilizes clare?s proprietary third generation vertical dmos process. the third generation process realizes world class, high voltage mosfet performance in an economical silicon gate process. the vertical dmos process yields a highly reliable device, particularly in difficult application environments such as telecommunications, security, and power supplies. one of the primary applications for the CPC5602 is as a linear regulator/hook switch for the litelink family of data access arrangements (daa) devices cpc5620a, cpc5621a, and cpc5622a. the CPC5602 has a typical on-resistance of 8 ? , a drain-to-source voltage of 350v, and is available in an sot-223 package. as with all mos devices, the fet structure prevents thermal runaway and thermal-induced secondary breakdown. pin number name 1gate 2 drain 3 source 4 drain parameter rating units drain-to-source voltage - v ds 350 v max on-resistance - r ds(on) 14 ? max power 2.5 w d g d s 4 1 23
www.clare.com 2 r07 CPC5602 parameter symbol conditions min typ max units gate-to-source off voltage v gs(off) i d = 2a, v ds =10v, v ds =100v -3.6 -2.62 -2 v drain-to-source leakage current i ds(off) v gs = -5v, v ds =190v - - 20 na v gs = -5v, v ds =350v - - 1 ? a drain current i d v gs = -2.7v, v ds =5v, v ds =50v - - 5 ma v gs = -0.57v, v ds =5v 130 - - ma on-resistance r ds(on) v gs = -0.35v, i ds =50ma - 8 14 ? gate leakage current i gss v gs =10v, v gs =-10v - - 0.1 ? a gate capacitance c iss v ds = v gs =0v - - 300 pf electrical characteristics @25 o c (unless otherwise specified) absolute maximum ratings are stress ratings. stresses in excess of these ratings can cause permanent damage to the device. functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. absolute maximum ratings @ 25oc thermal characteristics parameter symbol conditions min typ max units thermal resistance r ? jc - - - 14 oc/w parameter ratings units drain-to-source voltage (v ds ) 350 v gate-to-source voltage (v gs ) 20 v total package dissipation 2.5 w operational temperature -40 to +85 o c storage temperature -40 to +125 o c
CPC5602 www.clare.com 3 r07 performance data* *the performance data shown in the graphs above is typical of device performance. for guaranteed parameters not indicated in t he written speci? cations, please contact our application department. v ds (v) 012345 i d (a) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 output characteristics (t a =25oc) v gs =-0.5 v gs =-1 v gs =-1.5 v gs =-2 i d (a) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 on-resistance ( : ) 0 5 10 15 20 on-resistance vs. drain current (v gs =0v) i d (ma) 0 50 100 150 0 50 100 150 200 250 300 transconductance vs drain current (v ds =10v) t a =-40oc t a =25oc t a =125oc g fs (m ) v gs (v) -3.0 -2.5 -2.0 -1.5 -1.0 i d (ma) 0 50 100 150 200 250 transfer characteristics (v ds =10v) t a =125oc t a =25oc t a =-40oc temperature (oc) -40 -20 0 20 40 60 80 100 v gs(off) (v) -3.0 -2.9 -2.8 -2.7 -2.6 -2.5 -2.4 -2.3 v gs(off) vs. temperature (v ds =10v, i d =2 a) temperature (oc) -40 -20 0 20 40 60 80 100 on-resistance ( ) 4 5 6 7 8 9 10 11 12 on-resistance vs. temperature (v gs =0v, i d =100ma) v ds (v) 0 5 10 15 20 25 30 capacitance (pf) 0 50 100 150 200 250 300 capacitance vs. drain-source voltage (v gs =-5v) c iss c oss c rss temperature (oc) 0204060 80 100 120 power dissipation (w) 0 0.5 1.0 1.5 2.0 2.5 3.0 power dissipation vs. ambient temperature 4.0 3.5 140 160 v ds (v) 1 10 100 1000 i ds (a) 0.001 0.01 0.1 1 forward safe operating bias (v gs =0v, dc load, t c =25oc) limited by device channel saturation limited by device r ds(on)
www.clare.com 4 r07 CPC5602 manufacturing information moisture sensitivity all plastic encapsulated semiconductor packages are susceptible to moisture ingression. clare classified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, ipc/jedec j-std-020 , in force at the time of product evaluation. we test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. this product carries a moisture sensitivity level (msl) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard ipc/jedec j-std-033 . device moisture sensitivity level (msl) rating CPC5602c msl 1 esd sensitivity this product is esd sensitive , and should be handled according to the industry standard jesd-625 . reflow profile this product has a maximum body temperature and time rating as shown below. all other guidelines of j-std-020 must be observed. device maximum temperature x time CPC5602c 260oc for 30 seconds board wash clare recommends the use of no-clean flux formulations. however, board washing to remove flux residue is acceptable. since clare employs the use of silicone coating as an optical waveguide in many of its optically isolated products, the use of a short drying bake could be necessary if a wash is used after solder reflow processes. chlorine- or fluorine-based solvents or fluxes should not be used. cleaning methods that employ ultrasonic energy should not be used. rohs 2002/95/ec e 3 pb
clare, inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publica tion and reserves the right to make changes to specifications and product descriptions at any time without notice. neither circuit patent licenses nor indemnity are expressed or implied. exce pt as set forth in clare?s standard terms and conditions of sale, clare, inc. assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. the products described in this document are not designed, intended, authorized or warranted for use as components in systems in tended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of clare?s product may result in direct physical harm, injury, or dea th to a person or severe property or environmental damage. clare, inc. reserves the right to discontinue or make changes to its products at any time without notice. specification: ds-CPC5602-r07 ?copyright 2012, clare, inc. all rights reserved. printed in usa. 3/9/2012 for additional information please visit our website at: www.clare.com CPC5602 5 mechanical dimensions dimensions mm min / mm max (inches min / inches max) 6.705 / 7.290 (0.264 / 0.287) 0.229 / 0.330 (0.009 / 0.013) 0.914 min (0.036 min) 1.90 (0.075) 1.90 (0.075) 6.10 (0.24) 2.286 (0.090) 0.90 (0.035) 3.20 (0.126) 6.30 / 6.71 (0.248 / 0.264) 2.286 (0.090) 3.30 / 3.71 (0.130 / 0.146) 2.90 / 3.10 (0.114 / 0.122) 0.610 / 0.787 (0.024 / 0.031) 0.020 / 0.102 (0.0008 / 0.004) 0.864 / 1.067 (0.034 / 0.042) 4.597 (0.181) 1.549 / 1.803 (0.061 / 0.071) 1.499 / 1.981 (0.059 / 0.078) pcb land pattern pin 1 CPC5602c CPC5602c tape & reel dimensions mm (inches) embossment embossed carrier 177.8 dia (7.00 dia) top cover tape thickness 0.102 max (0.004 max) w=12.08 0.2 (0.476 0.008) b 0 =7.42 0.1 (0.292 0.004) a 0 =6.83 0.1 (0.269 0.004) p=8.03 0.1 (0.316 0.004) k 0 =1.88 0.1 (0.074 0.004) 2.00 0.05 (0.079 0.002) 4.00 0.1 (0.157 0.004) 1.75 0.1 (0.069 0.004) 5.50 0.05 (0.217 0.002)
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